1. Technical Field
Embodiments of the present disclosure may generally relate to semiconductor devices and a bit line pre-charge operation.
2. Related Art
Semiconductor memory devices may include a plurality of memory cells in which data are stored. The Semiconductor memory devices may also include word lines and bit lines which are used to select at least one of the plurality of memory cells and/or to transmit the data during a read operation or a write operation. The bit lines may be always pre-charged to have a predetermined voltage level in advance of the read operation or the write operation. That is, the bit lines may be pre-charged to a half of a core voltage before access of the data in order to reduce an access time.
As the plurality of memory cells are scaled down to increase the integration density of the semiconductor memory devices, a size of connection nodes between the bit lines and the memory cells has been continuously reduced. If the size of the connection nodes is reduced, a contact resistance value between the bit lines and the memory cells may increase. Due to the increase in the contact resistance value some characteristics (e.g., a data access time or a data write time) of the semiconductor memory devices are degraded. That is, if the contact resistance value between the bit lines and the memory cells increases, the data access time or the data write time of the semiconductor memory devices may also increase. Thus, it may be necessary to increase an activation time of any one selected from the word lines in order to stably store the data into selected memory cells. However, if the activation time of the word line increases, a pre-charge period of the bit lines may be reduced.